Large numbers of identical integrated circuits (ICs) such as microprocessors, memory devices, and digital signal processing devices are generally fabricated on a silicon wafer. Due to defects that may occur during fabrication, each IC (or “die”) on the wafer is typically separately tested or sorted by test equipment such as automatic test equipment (ATE) and probe cards. Probe cards may be capable of making temporary conductive contact to a single die or a small cluster of dice, and in limited applications, whole wafers. The ATE may complete the wafer-level test by sequentially stepping a probe card through the individual die or die-cluster locations across the wafer until all dice on the wafer have been tested. The test signals are provided to each die through input or input/output bond pads on each die, and the test results are monitored on output bond pads. The good die that pass the wafer-level test are then singulated and packaged typically by electrically connecting the bond pads to the package with bond wires, solder balls, or other contact structures. To accommodate the bonding wires or solder balls, the bond pads are generally very large relative to the circuit elements of the integrated circuit. Typical bond pad sizes are on the order of 100 um (micrometers)×100 um. The bond pads are also typically aligned in regular patterns such as peripherally along the outside perimeter of the die, in a grid pattern, or in a column or row generally through the center of the die (lead-on-center).
While wafer-“level” test is well established in the industry, there is no accepted means for wafer-“scale” test or wafer-“level” “burn-in.” Moreover, established probe technologies are limited to device AC testing at or below 1-2 GHZ frequencies. The present invention overcomes these limitations.
The bond pads allow each die separately to be functionally tested for specified timing parameters (AC parameters), DC parameters, and overall operation. When probing chips or wafers, it is important to have a planar set of probe contacts so that each probe contact can make simultaneous electrical contact to a respective chip contact. It is also important to have the contacts on the wafer coplanar. Typically, if the tips of the probe contacts do not lie in approximately the same plane, or if some of the contacts on the wafer are out of plane, more force must be exerted on the back of the probe in an effort to engage all of the probe contacts with the chip contacts. This typically leads to non-uniform forces between the tips of the probe contacts and the wafer contacts. If too much force is placed on any one probe contact, there is a potential to degrade the chip contacts, which can detrimentally affect device performance and consequently affect device yield. Planarity and uniform probe contact force are also important in order to have approximately the same ohmic resistance across all of the probe contacts so that the electrical signals have approximately the same level of integrity. Loss in signal integrity can detrimentally affect device performance and consequently affect device yield. In most cases, there can be hundreds of thousands of contacts across a single wafer. Maintaining similar ohmic probe to chip contact resistance is especially important for accurate testing of chips that are designed to be run at high speeds. For such high speed chips, it is also important to control the impedance of the probe tester (resistance, capacitance & inductance) as a whole to maintain the integrity of the electrical signals to allow the desired range of parametric testing.
In a conventional manufacturing process flow, following packaging, the ICs are subjected to what is referred to in the industry as a Burn-In (BI) process, in which the ICs are electrically activated simultaneously while subjected to temperature cycling over a period of hours to days. This burn-in process is used to accelerate and screen early life failures of the ICs, thus ensuring high reliability of the component. In this conventional process, the packaged ICs are inserted into an electrical socket which makes contact to the IC package pins. The burn-in sockets are mounted to large burn-in boards which are loaded into large thermal cycling ovens which can handle very large volumes of ICs. The burn-in sockets are designed to take advantage of the large pin spacing and pin size in comparison to the finer bond-pad pitch and size as described previously. Although at a very high cost to the electronics industry, the relatively large pin size and spacing and relatively low pin count and high planarity found within a single die, has enabled the single-die-per-socket IC burn-in approach to be widely adopted.
One disadvantage of the current approach to IC burn-in is high cost. Due to the requirement for custom burn-in sockets for each new IC or IC package design, short product design lifetime (as little as 12 months) and the long burn-in cycle time, the burn-in process requires a huge investment in burn-in sockets and processing time to support the volumes of ICs which are manufactured today.
Another disadvantage of this method of IC burn-in is that it commonly must be done only after packaging of the IC or in a few instances, to singulated bare-die. While this technique can be used for conventional single-die packaging, or multi-chip packaging, this technique cannot be used when die-to-wafer or wafer-to-wafer integration of ICs is required. To enable die-to-wafer or wafer-to-wafer integration, a means to do Wafer-Level-Burn-In and Test (WLBI, WLBIT) has been proposed.
While acceptable means for wafer-level single/clustered die test and single-die burn-in have been employed, the industry has not yet found an acceptable means of employing wafer-“level” burn-in and wafer-“scale” test.
Wafer-level burn-in has not been adopted because of the lack of an acceptable solution to the problems described above, and in addition:
1. Difficulty in achieving satisfactorily uniform ohmic resistance across the wafer.
2. Due to ohmic resistance non-uniformity, and lack of contact redundancy per pad, there is no way to ensure all die are being activated, and hence, there is no way to ensure all die have been adequately burned-in, thus allowing potential early life failures to escape into the field. Because there are tens of thousands of contact pads on a wafer, which all must be contacted, this is a major problem.
3. High compressive forces are needed to compress prior-art micro-spring probe contacts in order to make good, low-ohmic resistance contact. This high compressive force damages the IC bond pad, or worse can damage the IC's dielectric layers which can be extremely fragile, especially with the recent adoption of low-k dielectric materials. In the case of bumped ICs used for chip-scale packaging, no damage to the bump surface is allowed, preventing the use of micro-spring probe cards altogether. In specific applications, there are probe contacts which contact and cut into two opposing sides of an interconnect bump, similar in principle, to a pair of tweezers. This configuration is limited to only large ball sizes/pitches such as in Ball-Grid-Array (BGA) packaged ICs.
4. When multiplying the high compressive force per contact by tens of thousands of contacts, the mechanical fixturing required to maintain this high compressive force between the wafer and probe card would be excessively large, heavy and costly for wide use in wafer-level burn-in, where ICs must be cycled for up to days within a temperature cycle oven.
5. Excessive initial cost and damage-induced cost associated with intricate, fragile mechanical structure based probe cards, such as micro-spring or membrane or Micro-Electro-Mechanical-Systems (MEMS) based probe cards, has prevented these prior-art technologies from being accepted.
What is needed is a method for wafer-level burn-in and test which resolves these problems, and provides advantages over other prior approaches proposed. These prior approaches include:
1. Epoxy-ring cantilever spring contact probe cards—use limited by variation in contact force, limited contact point aerial density due to the space required for the epoxy ring, high cost intricate manual fabrication, high electrical inductance, and IC pad pitch or pattern limited to low density pad arrays. This prior art is also known to cause severe damage to IC pads, referred to in the industry as “pad scrubbing”.
2. Micro-spring probe-cards fabricated through either mechanical formation or electroplated micro-mechanical assembly—use limited by high cost, susceptibility to damage, limited to lower bond pad aerial density devices due to the minimum achievable micro-spring size, limited aerial coverage (cannot achieve full wafer-scale probing), limited or no repair-ability, susceptibility to causing IC bond pad damage through micro-indentation. Micro-indentation is unacceptable for bumped ICs, especially those used in chip-scale packaging.
3. MEMS probe card having micro-machined mechanical probes bonded to rigid substrates. Limited range or amount of probe compliance (cannot scale to full-wafer probing due to insufficient range of compliance), high cost due to many intricate fabrication steps, limited aerial coverage difficulty to repair, susceptibility to causing IC bond pad damage.
4. Membrane probe cards having micro indenting tips deposited onto the surface of a flexible circuit board—limited probe compliance, high cost, no full-wafer probing capability, high cost, limited probe contact force resulting in poor IC pad contact reliability.
Each of these methods is limited to single or small-area probing due to the highly complex, intricately assembly of microstructures associated with their application to probe cards. Due to their complexity, each prior-art method suffers from low yield and associated high cost when attempts are made to fabricate them in large arrays or at high aerial densities.